Leakage current runaway is a catastrophic phenomenon that occurs in MOSFET devices during dormant mode when a MOSFET device is biased with full operating voltage (Vdd) across source and drain nodes while gate voltage is switched off. Normally, the leakage current in a dormant MOSFET device does not change with time. However, if the device channel length is sufficiently short, the leakage current, especially the drain induced barrier lower (DIBL) leakage current, will increase over time. In such cases, this DIBL current can possess enough energy to cause impact ionization inside the transistor channel and damage the device, resulting in a decrease in threshold voltage. A lowered threshold voltage prompts a further increase in DIBL leakage current, and subsequently, a chain reaction takes place with a positive feedback that eventually results in leakage current runaway.
Leakage current runaway is becoming a serious concern due to the ever increasing use of very short channels and extended dormant mode in high speed designs. The details of the leakage current runaway mechanism have been reported in a paper titled “Degradation and Recovery of NMOS Subthreshold Leakage Current by Off-state Hot Carrier Stress” in 2006 ICCDCS. As discovered by the authors of this paper, the increase of the leakage current can be recovered by switching devices from dormant mode into active mode for a short period of time.